Fractional divider with duty cycle regulation and low subharmonic content

ABSTRACT

Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.

TECHNICAL FIELD OF THE DISCLOSURE

The present disclosure generally relates to electronics, and moreparticularly to frequency divider circuitry (e.g., at a frequencysynthesizer).

BACKGROUND

Both, systems used for wireless communication such as Long TermEvolution (LTE) and 5th generation (5G), and systems used for cablecommunication such as cable television networks, are radio systems inthat they transmit and receive signals in the form of electromagneticwaves in the radio frequency (RF) range of approximately 3 kiloHertz(kHz) to 300 gigaHertz (GHz).

Frequency synthesizers are commonly used in wireless communicationsystems for generating a range of frequencies from a single oscillator.In recent years, the number of different wireless bands and standards inwhich a mobile device may communicate has increased dramatically.Different wireless communication standards may utilize differentfrequency ranges. For example, 5G alone may operate over frequency bandsranging from sub-6 gigahertz (GHz) to tens of GHz. Often amulti-standard system-on-chip (SOC) may utilize a frequency synthesizerto provide a wide range of frequencies. In some examples, amulti-standard SOC may utilize a voltage-controlled oscillator (VCO)having an octave tuning range with a frequency synthesizer, and thefrequency synthesizer may be followed by a power of 2 frequency division(e.g., 1, 2, 4, 8, 16, etc.) to provide a wide range of frequencies.

VCO phase noise can be critical and often does not follow 20*log 10(Fosc) for wideband designs, where Fosc represents the frequency of theVCO output signal. In some examples, degradation can be as high as 12decibel (dB)/octave. A narrow band VCO may generally provide a lowerphase noise. Thus, in some examples, an octave range may be provided byusing multiple VCOs (e.g., narrow band VCOs) with different tuningfrequency ranges. When using multiple VCOs, the appropriate VCO may beturned on and multiplexed to the output based on the desired frequency.While utilizing multiple VCOs may provide a better performance, it maybe inefficient in terms of die area. For instance, VCOs may be large insize due to inductor and capacitor arrays at the VCOs, and often onlyone out of a number of VCOs is turned on at a time. As process shrinks,transistors have become smaller in size, but metallization have not beenimproved, and VCO area may continue to be dominated by inductor andcapacitor arrays.

BRIEF DESCRIPTION OF THE DRAWINGS

To provide a more complete understanding of the present disclosure andfeatures and advantages thereof, reference is made to the followingdescription, taken in conjunction with the accompanying figures, whereinlike reference numerals represent like parts, in which:

FIG. 1 is a block diagram illustrating an exemplary frequencysynthesizer in which a duty cycle regulated, balanced fractional divideras disclosed herein may be implemented, according to some embodiments ofthe present disclosure;

FIG. 2 is a schematic diagram illustrating exemplary fractional dividercircuitry;

FIG. 3 is a timing diagram illustrating signals in exemplary fractionaldivider circuitry;

FIG. 4 is a block diagram illustrating an exemplary duty cycleregulated, balanced fractional divider circuitry, according toembodiments of the present disclosure;

FIG. 5 is a schematic diagram illustrating exemplary balanced fractionaldivider circuitry, according to embodiments of the present disclosure;

FIG. 6 is a timing diagram illustrating signals in exemplary balancedfractional divider circuitry, according to some embodiments of thepresent disclosure;

FIG. 7 is a schematic diagram illustrating exemplary duty cyclecorrection circuitry, according to embodiments of the presentdisclosure;

FIG. 8 is a timing diagram illustrating signals in exemplary duty cyclecorrection circuitry, according to embodiments of the presentdisclosure;

FIG. 9 is a schematic diagram illustrating exemplary duty cyclecorrection circuitry, according to embodiments of the presentdisclosure;

FIG. 10 is a timing diagram illustrating signals in an exemplary dutycycle correction circuitry, according to embodiments of the presentdisclosure; and

FIG. 11 is block diagram illustrating an exemplary RF device, accordingto embodiments of the present disclosure.

DESCRIPTION OF EXAMPLE EMBODIMENTS OF THE DISCLOSURE

Overview

The systems, methods and devices of this disclosure each have severalinnovative embodiments, no single one of which is solely responsible forall of the desirable attributes disclosed herein. Details of one or moreimplementations of the subject matter described in this specificationare set forth in the description below and the accompanying drawings.

As described above, while utilizing multiple narrow band VCOs to providea wide frequency range can be better for performance, it can be costlyin terms of die area. One approach to eliminating one or more VCO coresyet providing the same wide frequency range is to use a fractionaldivider such as a frequency divider with a frequency division ratio of1.5, which may be referred to as a 1.5 frequency divider. Alternatively,utilizing a 1.5 frequency divider may allow the use of narrower rangeVCO cores in a given area. However, a 1.5 frequency divider maygenerally output a clock signal with a non-50% duty cycle and/or withsubharmonic spurs or distortion (e.g., at half the frequency of theclock signal), which may be undesirable for many systems. Accordingly,there is a need to provide 1.5 frequency divider with improvedperformance.

The present disclosure describes mechanisms for providing a fractionalfrequency divider with regulated duty cycle and a low subharmonicdistortion. In one aspect of the present disclosure, an apparatus mayinclude frequency divider circuitry including a first node to receive aninput signal (e.g., a reference clock signal or a VCO signal) andfractional divider circuitry to generate a first signal by dividing afrequency of the input signal based on a frequency-division ratio (e.g.,of 1.5). The first signal may be referred to as a frequency-dividedsignal. The first signal may have a first series of pulses with adjacentpulses triggered by opposite edges (e.g., rising edges and fallingedges) of the input signal. Because rising edges and the falling edgesof the input signal may be imbalanced (e.g., having different noisecharacteristics), the first signal can have subharmonic spurs (e.g., athalf the frequency of the input signal).

To reduce or cancel the subharmonic spurs, the frequency dividercircuitry may further include balance divider circuitry to generate asecond signal having a same phase as the output (e.g., the first signal)of the fractional divider circuitry but triggered on opposite edges ofthe input signal. That is, the second signal may have a second series ofpulses aligned (e.g., in time and/or phase) to the first series ofpulses. In some aspects, the balance divider circuitry may include areplica circuit replicating a first circuit of the fractional dividercircuitry, but the replica circuit may be triggered by opposite edges ofthe input signal than the first circuit. The frequency divider circuitrymay further include a second node to combine the first signal and thesecond signal such that the combined signal may have at least a reducedsubharmonic distortion than the first signal.

In some aspects, the fractional divider circuitry may include a firstsignal selection circuitry (e.g., the first circuit). The balancedivider circuitry may have a second signal selection circuitry (e.g.,the replica circuit) triggered by opposite edges of the input signalthan the first signal selection circuitry. In some aspects, the firstsignal selection circuitry may be a first multiplexer, and the secondsignal selection circuitry may be a second multiplexer, where the firstand second multiplexers may be of the same multiplexer cell type (e.g.,same circuit topology), and thus may have the same switchingcharacteristics. Each of the first signal selection circuitry and thesecond signal selection circuitry may have a respective first input, arespective second input, and a respective output, where the first inputor the second input may be selectively coupled to the output at anygiven time. To reduce or cancel the subharmonic spurs, the first signalselection circuitry may switch from selecting the first respective inputto selecting the second respective input responsive to one of a firstrising edge or a first falling edge of the input signal, and the secondsignal selection circuitry may switch from selecting the respectivefirst input to selecting the respective second input responsive to theother one of the first rising edge or the first falling edge of theinput signal.

Additionally or alternatively, the fractional divider circuitry caninclude duty cycle correction circuitry to adjust the duty cycle of afrequency-divided signal (e.g., the first signal or the combined firstand second signal with the reduced subharmonic content) and provide aduty cycle-adjusted signal (e.g., with a 50% duty cycle) as output. Theduty cycle correction circuitry can be in the form of a delay-lockedloop (DLL). In some aspects, the DLL may generate a rising edge of theduty cycle-adjusted signal from a rising edge of the frequency-dividedsignal, and generate a falling edge of the duty cycle-adjusted signalthrough active feedback. To that end, the DLL may include a filter(e.g., a low-pass filter) to output a direct current (DC) component(e.g., an average) of the frequency-divided signal. The DLL may furtherinclude an amplifier (e.g., a single-ended amplifier) having a firstinput to receive the DC component of the frequency-divided signal, asecond input to receive a reference voltage, and an output to output anerror signal. The error signal may correspond to a voltage differencebetween the DC component of the frequency-divided signal and thereference voltage. As such, to regulate the frequency-divided signal toa 50% duty cycle, the reference voltage may be set to about half of thesupply voltage. Alternatively, the reference voltage may be set to anysuitable voltage level according to a desired duty cycle. The DLL mayfurther include a variable delay line controlled by the error signal togenerate a feedback signal. In one aspect, the duty cycle correctioncircuitry may generate the falling edge of the duty cycle-adjustedsignal further from a rising edge of the feedback signal. In anotheraspect, the DLL may generate the falling edge of the duty cycle-adjustedsignal further by gating a falling edge of the frequency-divided signalby the feedback signal.

In some aspects, the apparatus may further include a phase-locked loop(PLL) including a VCO and the frequency divider circuitry coupled to theVCO. The PLL may be part of a frequency synthesizer, where the apparatusmay further include an integer divider circuitry to divide the balancedand/or duty cycle-regulated frequency-divided signal. In some aspects,the apparatus may be a radio transceiver, for example, a radiotransceiver integrated circuit (IC). For instance, the frequency dividercircuitry may be in an RF domain, a digital input/output (IO) domain, ora clock tree domain of the IC. In some instances, the radio transceiverIC may include multiple balanced, and/or duty cycle-regulated frequencydivider circuitries as disclosed herein, each in a different domain(e.g., RF domain, digital IO domain, and/or clock tree domain).

The systems, schemes, and mechanisms described herein advantageouslyprovide a fractional frequency divider with reduced subharmonicdistortion and/or a regulated duty cycle (e.g., of 50%). In one example,the improved fractional frequency divider may enable an IC to utilize afewer number of VCO cores to provide same wide frequency range, and thuscan reduce die area and cost. In another example, the improvedfractional frequency divider may enable an IC to utilize VCO(s) with areduced tuning range (e.g., narrower band) to achieve the same widefrequency range with a lower phase noise. In yet another example, theimproved fractional frequency divider may reduce the maximum requiredVCO frequency. For instance, a transmitter that requires a 12 GHzdigital-to-analog converter (DAC) clock for transmission and a 9 GHzanalog-to-digital converter (ADC) clock for reception may utilize an 18GHz VCO rather than a 24 GHz VCO, for example, when frequency divider ofdivide-by-powers-of-two only are used following a PLL. In general, thebalanced, duty cycle-regulated fractional divider circuitry can be usedin any suitable processing domains and/or in any suitable IC devices.

Example Frequency Synthesizer

FIG. 1 is a block diagram illustrating an exemplary frequencysynthesizer 100 in which a duty cycle regulated, balanced fractionaldivider as disclosed herein may be implemented, according to someembodiments of the present disclosure. In some aspects, the frequencysynthesizer 100 may be part of a RF transceiver (e.g., the RF device2200 of FIG. 11 ) or transceiver IC. In one example, the frequencysynthesizer 100 may operate in an RF domain to support ADC conversion,DAC conversion, frequency downconversion, or frequency upconversion. Inanother example, the frequency synthesizer 100 may operate in a digitalIO domain to support digital data input to a peripheral device of thetransceiver and/or output from a peripheral device of the transceiver.In another example, the frequency synthesizer 100 may operate in a clocktree domain to provide various clock signals for operations at thetransceiver. As shown, the frequency synthesizer 100 may include a PLL101. The PLL 101 may include phase detector circuitry 110, charge pumpcircuitry 120, loop filter circuitry 130, VCO circuitry 140, frequencydivider (FDIV) circuitry 150, and multiplexer (MUX) circuitry 152 in aforward path, and multi-modulus frequency divide (MMD) circuitry 160 anddelta-sigma modulator (DSM) circuitry 170 in a feedback path.

The phase detector circuitry 110 may receive an input reference clocksignal 102, shown as CLK_(REF), and detect the difference in phasebetween the reference clock signal 102 and a feedback signal 162. Thephase detector circuitry 110 may generate phase error correction orcontrol signals, shown as UP and DOWN, indicative of whether the phaseof the feedback signal 162 leads or lags the phase of the referenceclock signal 102. The control signals may be provided to control thecharge pump circuitry 120, which may sink current when receiving a“DOWN” pulse and sources current when receiving an “UP” pulse. Theoutput pump current of the charge pump circuitry 120 may be provided tothe loop filter 130, which may generate a control voltage from thecharge pump current. The control voltage output by the loop filter 130may be provided to the VCO circuitry 140.

In some instances, the VCO circuitry 140 may include multiple VCO cores(e.g., 2, 3, 4, or more). Each VCO core may oscillate at a higher orlower frequency based on the control voltage level provided by the loopfilter 130. Further, each VCO core may cover a different frequency rangeor tuning range. At any one time, one of the VCO core may be active. Forexample, the frequency synthesizer 100 may be part of a transceiver, anda VCO core may be selected depending on the selected RF channel wherethe transceiver desires to operate at a particular time. In someexamples, the active VCO core can be selected by switches. The selectedVCO core may stabilize when the reference clock signal 102 and thefeedback clock signal 162 are at the same phase and frequency. Ingeneral, any type of VCO can be used in the frequency synthesizer 100.For example, in one embodiment, each VCO core may include a switchedcapacitor array and a switched inductor array. Other VCO implementationscan be used in other embodiments.

The selected VCO core from the VCO circuitry 140 may output a clocksignal with a frequency controlled by the control voltage output by theloop filter 130. The VCO output signal may be provided to the frequencydivider circuitry 150. In some aspects, the frequency divider circuitry150 may be a fractional divider circuitry, for example, performingfrequency-division by a fractional division ratio (e.g., a ratio of 1.5or any other suitable fractional ratio). In some aspects, the frequencydivider circuitry 150 may be implemented with duty cycle correction orregulation and/or subharmonic cancellation as disclosed herein. Themultiplexer circuitry 152 may selectively couple the frequency-dividedsignal output by the frequency divide circuitry 150 or the VCO outputsignal to the output as an output clock signal 104, shown as CLK_(OUT).The selection may be based on a selection signal, which may depend onthe desired output clock frequency (e.g., whether to use a divide by 1.5or a divide by 1 frequency division). The output clock signal 104 may beprovided to the MMD 160.

The MMD 160 may divide the output clock signal 104 by a multi-modulusdivider division factor M to provide the feedback signal 162. Forexample, the output clock signal 104 may have a frequency represented byFout, and the feedback signal 162 may have a frequency represented byFcomp, where Fcomp=Fout/M. The multi-modulus divider division factor Mmay be controlled by the DSM 170, which may in turn be controlled by acontrol signal 106, shown as CTRL. In some instances, the control signal106 may have an integer portion N and a fractional portion f (e.g.,represented by N.f), and the DSM 170 may provide a sequence of integersNdiv close in value to the divide signal N.f, in such a way that theaverage value of Ndiv equals the divide signal N.f. In some aspects, thefrequency synthesizer 100 may further include a power-of-2 frequencydivider 154 to frequency-divide the output clock signal 104 bypower-of-2 division ratio (e.g., 1, 2, 4, 8, 16, etc.) to achievevarious frequencies for the final output clock signal 156.

Example Fractional Divider Circuitry

FIG. 2 is a schematic diagram illustrating exemplary fractional dividercircuitry 200. In some aspects, the frequency synthesizer 100 of FIG. 1may include the fractional divider circuitry 200 as part of thefrequency divider circuitry 150. At a high level, the fractional dividercircuitry 200 may receive an input signal 201 at an input node (shown asIN), divide the frequency of the input signal 201 by a frequencydivision ratio of 1.5 to generate a frequency-divided signal, andprovide the frequency-divided signal as an output signal 203 at anoutput node (shown as OUT). The input signal 201 may include a series ofinput pulses at a certain frequency, Fin (e.g., as shown by 302 of FIG.3 ). The output signal 203 may include a series of output pulses at afrequency of Fin/1.5 (e.g., as shown by 306 of FIG. 3 ).

As shown in FIG. 2 , the fractional divider circuitry 200 may includemain divider circuitry 202 and a feedback circuitry 204. The maindivider circuitry 202 may include dual edge-triggered circuitry 210, amultiplexer 220 (e.g., signal selection circuitry), an AND gate 230, andan inverter 240. The dual edge-triggered circuitry 210 may include afirst latch 212 and a second latch 214. The first latch 212 may includea data terminal (shown by “D”) coupled to the output of the AND gate230, an enable terminal (shown by “E”) coupled to the input node toreceive an inversion of the input signal 201, and an output terminal(shown by “Q”) coupled to a first input (shown by “S1”) of themultiplexer 220. The second latch 214 may include a data terminal (shownby “D”) coupled to the output of the AND gate 230, an enable terminal(shown by “E”) coupled to the input node to receive the input signal201, and an output terminal (shown by “Q”) coupled to a second input(shown by “S2”) of the multiplexer 220. The multiplexer 210 mayselectively couple the first input or the second input of themultiplexer 220 to the output node OUT. The AND gate 230 may include afirst input coupled to the feedback circuitry 204 (e.g., to receive afeedback signal 205 (shown as FB)) and a second input coupled to theoutput of the inverter 240, where the input of the inverter 240 iscoupled to the output node OUT.

The feedback circuitry 204 may include dual edge-triggered circuitry250, a multiplexer 260 (e.g., signal selection circuitry), and aninverter 270. The dual edge-triggered circuitry 250 may include a thirdlatch 252 and a fourth latch 254. The third latch 252 may include a dataterminal (shown by “D”) coupled to the output node, an enable terminal(shown by “E”) coupled to the input node to receive an inversion of theinput signal 201, and an output terminal (shown by “Q”) coupled to afirst input (shown by “S1”) of the multiplexer 260. The fourth latch 254may include a data terminal (shown by “D”) coupled to the output nodeOUT, an enable terminal (shown by “E”) coupled to the input node toreceive the input signal 201, and an output terminal (shown by “Q”)coupled to a second input (shown by “S2”) of the multiplexer 260. Themultiplexer 260 may selectively couple the first input or the secondinput of the multiplexer 260 to the output of the multiplexer 260. Theoutput of the multiplexer 260 is coupled to the input of the inverter270. The output of the inverter 270 is coupled to the main dividercircuitry 202 to provide the feedback signal 205 to the main dividercircuitry 202.

In operation, at the main divider circuitry 202, the first latch 212 andthe second latch 214, each latches the output of the AND gate 230 to therespective output terminals (Q) based on triggers at the respectiveenable terminal (E). As shown, the first latch 212 is triggered on thefalling edges of the input signal 201, whereas the second latch 214 istriggered on the rising edges of the input signal 201. The multiplexer220 selects the output of the first latch 212 (at the first input S1)when the input signal 201 is in a logic high state and selects theoutput of the second latch 214 (at the second input S2) when the inputsignal 201 is in a logic low state.

The feedback circuitry 204 may keep track of which edge of the inputsignal 201 was being triggered last to generate the output signal 203and may switch between the rising edges and the falling edges of theinput signal 201 at every half cycle of the input signal 201. To thatend, at the feedback circuitry 204, the third latch 252 and the fourthlatch 254, each latches the output signal 203 to the respective outputterminal (Q) based on triggers at the respective enable terminal (E). Asshown, the third latch 252 is triggered on the falling edge of the inputsignal 201, whereas the fourth latch 254 is triggered on the rising edgeof the input signal 201. The multiplexer 260 selects the output of thethird latch 252 (at the first input S1) when the input signal 201 is ina logic high state and selects the output of the fourth latch 254 (atthe second input S2) when the input signal 201 is in a logic low state.The output of the multiplexer 260 is inverted by the inverter 270 toprovide the feedback signal 205. The AND gate 230 applies an ANDoperation to the feedback signal 205 and the output signal 203 invertedby the inverter 240 to control inputs to the first latch 212 and thesecond latch 214. The resulting output signal 203 at the output node mayinclude a series of pulses with adjacent pulses triggered by oppositeedges of the input signal 201.

FIG. 3 is a timing diagram 300 illustrating signals in exemplaryfractional divider circuitry 200 of FIG. 2 . In FIG. 3 , the x-axis mayrepresent time in some arbitrary units. The plot 302 shows the inputsignal 201 of the fractional divider circuitry 200. The plot 304 showsthe signal at the output of the first latch 212 triggered by the fallingedges (shown by down arrows) of the input signal 201. The plot 306 showsthe signal at the output terminal of the second latch 214 triggered bythe rising edges (shown by up arrows) of the input signal 201. The plot308 shows the signal at the output of the multiplexer 220, where themultiplexer 220 generates the output signal by alternating the selectionfrom the output of the first latch 212 and the output of the secondlatch 214. As shown by the dotted arrows, the output of the multiplexer220 (corresponding to the output signal 203) includes a series of pulseswith adjacent pulses triggered by opposite edges of the input signal 201at the input node of the fractional divider circuitry 200. Morespecifically, to provide the frequency division ratio of 1.5, when afirst pulse of the output signal 203 is triggered by a rising edge ofthe input signal 201, an adjacent pulse prior to or after the firstpulse is triggered by a falling edge the input signal 201, where therising edge and the falling edge of the input signal 201 used for thetriggers are spaced apart from each other by 1.5 cycle time of the inputsignal 201.

As can be seen from FIG. 3 , while the fractional divider circuitry 200can provide a frequency-divided signal (corresponding to the output atthe multiplexer 220 or the output signal 203) from the input signal 201with a 1.5 frequency division ratio, the duty cycle of thefrequency-divided signal is less than 50% (e.g., about 33%). However, itmay be desirable to have clock signals with a 50% duty cycle for manysystems. As an example, some systems (e.g., sequential logic circuits)may use both rising edges and falling edges of a clock signal, and thusmay be sensitive to the duty cycle of the clock signal. Further, becausethe rising edges and the negative edges of the input signal 201 can havedifferent noise characteristics and delays in the fractional dividercircuitry 200 and some pulses in the output signal 203 are triggered byrising edges of the input signal 201 while some other pulses in theoutput signal 203 are triggered by falling edges of the input signal201, the output signal 203 can have subharmonic components ordistortion. As an example, if the input signal 201 has a frequency of 12GHz and the output signal 203 has a frequency of 8 GHz (after the 1.5frequency division), the output signal 203 may include subharmonicdistortion or spurs at 4 GHz away from the output frequency of 8 GHz.That is, the output signal 203 may have subharmonic components may be atabout 4 GHz and 12 GHz. The subharmonic distortion can causeinterference or noise in other signal paths of the system that uses thefractional divider circuitry 200.

Accordingly, the present disclosure provides techniques for regulatingor correcting the duty cycle of the fractional divider circuitry 200and/or reducing or cancelling subharmonic distortion in the fractionaldivider circuitry 200.

Example Duty Cycle Regulated, Balanced Fractional Divider Circuitry

FIG. 4 is a block diagram illustrating an exemplary duty cycleregulated, balanced fractional divider circuitry 400, according toembodiments of the present disclosure. In some aspects, the frequencysynthesizer 100 of FIG. 1 may include the duty cycle regulated, balancedfractional divider circuitry 400 as part of the frequency dividercircuitry 150. The duty cycle regulated, balanced fractional dividercircuitry 400 may include a frequency divider circuitry 410 followed byduty cycle correction circuitry 420. The frequency divider circuitry 410may include balance divider circuitry 412 and the fractional dividercircuitry 200 of FIG. 2 .

The duty cycle regulated, balanced fractional divider circuitry 400 mayreceive an input clock signal 402 represented by CLK_(REF). Thefractional divider circuitry 200 may frequency-divide the input clocksignal 402 by a fractional frequency division ratio (e.g., of 1.5 asdiscussed above with reference to FIGS. 2-3 ) to provide afrequency-divided signal. The balance divider circuitry 412 may cancelor at least reduce subharmonic distortion in the frequency-dividedsignal as will be discussed more fully below with reference to FIGS. 5-6. That is, the frequency divider circuitry 410 may output a balancedfrequency-divided signal 403, which may include at least a reducedsubharmonic distortion compares to the frequency-divided signal (e.g.,the output signal 203) generated by the fractional divider circuitry200. The duty cycle correction circuitry 420 may adjust a duty cycle ofthe balanced frequency-divided signal 403 to provide an output clocksignal 404 represented by CLK_(OUT), for example, with a 50% duty cycle,as will be discussed more fully below with reference to FIGS. 7-10 .

In general, a fractional frequency divider may include one of thebalance divider circuitry 412 or the duty cycle correction circuitry420. For example, a fractional frequency divider can include the balancedivider circuitry 412 but not the duty cycle correction circuitry 420.Alternatively, a fractional frequency divider can include the duty cyclecorrection circuitry 420 and not the balance divider circuitry 412. Inother examples, a fractional frequency divider may include both thebalance divider circuitry 412 and the duty cycle correction circuitry420 as shown in FIG. 4 . Further, while FIG. 4 illustrates the frequencydivider circuitry 410 utilizing the fractional divider circuitry 200 forfractional frequency division, the frequency divider circuitry 410 mayutilize any suitable frequency divider circuitry.

FIG. 5 is a schematic diagram illustrating exemplary balanced fractionaldivider circuitry 500, according to embodiments of the presentdisclosure. In some aspects, the frequency synthesizer 100 of FIG. 1 mayinclude the balanced fractional divider circuitry 500 as part of thefrequency divider circuitry 150. The balanced fractional dividercircuitry 500 may include balance divider circuitry 502 and thefractional divider circuitry 200 of FIG. 2 . In some aspects, thebalance divider circuitry 412 of FIG. 4 may implement subharmoniccancellation as shown in the balance divider circuitry 502.

In FIG. 5 , the balance divider circuitry 502 may replicate the maindivider circuitry 202. As shown, the balance divider circuitry 502 mayinclude dual edge-triggered circuitry 510, a multiplexer 520 (e.g.,signal selection circuitry), an AND gate 530, and an inverter 540similar to the dual edge-triggered circuitry 210, the multiplexer 220,the AND gate 230, and the inverter 240, respectively, and arranged in asubstantially similar arrangement as in the main divider circuitry 202.The dual edge-triggered circuitry 510 may include a fifth latch 512 anda sixth latch 514. Similar to the first latch 212 and the second latch214, the fifth latch 512 and the sixth latch 514 may each latch theoutput of the AND gate 530 to a respective output terminal (Q) based ontriggers at a respective enable terminal (E), where the AND gate 530inputs are coupled to the feedback signal 205 and the output of theinverter 540. However, to balance the different noise characteristics ordelays between the rising edges and the negative edges of the inputsignal 201, the triggering at the fifth latch 512 and the sixth latch514 and the selection at the multiplexer 520 may be responsive toopposite edges of the input signal 201 than the triggering at the firstlatch 212 and the second latch 214 and the selection at the multiplexer220.

For instance, the fifth latch 512 is triggered on the rising edges ofthe input signal 201 in contrast to the first latch 212 triggered on thefalling edges of the input signal 201. Similarly, the sixth latch 514 istriggered on the falling edges of the input signal 201 in contrast tothe second latch 214 triggered on the rising edges of the input signal201. Further, the multiplexer 520 selects the first input S1 when theinput signal 201 has a logic low level in contrast to the multiplexer220 selecting the first input S1 when the input signal 201 has logichigh level. Similarly, the multiplexer 520 selects the second input S2when the input signal 201 has a logic high level in contrast to themultiplexer 220 selecting the second input S2 when the input signal 201has logic low level.

Phrased differently, the multiplexer 520 may switch or transition fromselecting the first input S1 to selecting the second input S2 responsiveto a rising edge of the input signal 201 in contrast to the multiplexer220 switching from selecting the first input S1 to selecting the secondinput S2 responsive to a falling edge of the input signal 201.Similarly, the multiplexer 520 may switch from selecting the secondinput S2 to selecting first input S1 responsive to a falling edge of theinput signal 201 in contrast to the multiplexer 220 switching fromselecting the second input S2 to selecting the first input S1 responsiveto a rising edge of the input signal 201. In other words, themultiplexer 520 is triggered by opposite edges of the input signal 201than the multiplexer 220 to select between the first input S1 and thesecond input S2.

Triggering the fifth latch 512 and the sixth latch 514 on rising edgesand falling edges of the input signal 201, respectively, and arrangingthe multiplexer 520 to select the output of the fifth latch 512 and theoutput of the sixth latch 514 based on the input signal 201 having a lowlogic level and a high logic level, respectively, the balance dividercircuitry 502 may generate an output signal 503 (at the output of themultiplexer 520) having a series of pulses aligned (e.g., time-alignedand/or phase-aligned) to the series of pulses in the output signal 203of the fractional divider circuitry 200 (e.g., as shown by 614 of FIG. 6). The output signal 503 of the balance divider circuitry 502 and theoutput signal 203 of the fractional divider circuitry 200 may becombined or summed at the node N1 to provide the output signal 505 atthe output node OUT.

In some aspects, the multiplexer 520 at the balance divider circuitry502 and the multiplexer 220 at the main divider circuitry 202 may havethe same internal circuit topology or same IC multiplexer cell type. Assuch, if there are any systematic differences (e.g., different delays)in switching from the first input S1 to the second input S2 versusswitching from the second input S2 to the first input S1, having themultiplexer 520 triggered on opposite edges of the input signal 201 thanthe multiplexer 220 can balance these differences. Balancing thesedifferences can in turn cancel or reduce subharmonic component in theoutput signal 503 at the output node. That is, the output signal 505obtained by combining the output signal 503 of the output signal 203 canhave a reduced subharmonic distortion or spur compared to the outputsignal 203 alone. In some examples, the inclusion of the balance dividercircuitry 502 can suppress a subharmonic spur by 40 dB (e.g., a powerratio of signal to a carrier signal) or more. That is, the output signal503 can have a subharmonic spur (at a certain subharmonic frequency)that is about 40 dB lower than a subharmonic spur (at the samesubharmonic frequency) in the output signal 203.

While FIG. 5 illustrates the balance divider circuitry 502 replicatingthe entire main divider circuitry 202, aspects are not limited thereto.For example, in some aspects, the balance divider circuitry 502 mayreplicate a portion of the main divider circuitry 202. In other words,the balance divider circuitry 502 may include a replica circuitreplicating a first circuit of the main divider circuitry 202 and thereplica circuit may be arranged to be triggered on opposite edges of theinput signal 201 compared to the first circuit to balance the differentnoise characteristics or delays between the rising edges and thenegative edges of the input signal 201 and thereby reducing subharmonicspurs. In an example, the first circuit may correspond to themultiplexer 220, and the replica circuit may be a multiplexer in whichthe selection is triggered by opposite edges of the input signal 201than the multiplexer 220. For instance, the replicated multiplexer (thereplica circuit) may be connected in parallel with the multiplexer 220.

FIG. 6 is a timing diagram 600 illustrating signals in the balancedfractional divider circuitry 500 of FIG. 5 , according to someembodiments of the present disclosure. In FIG. 6 , the x-axis mayrepresent time in some arbitrary units. The plot 602 illustrates theinput signal 201 at the input node (IN) of the balanced fractionaldivider circuitry 500. The plots 604, 606, and 608 show signals at thefirst input S1 (output of the first latch 212), second input S2 (outputfor the second latch 214), and output, respectively, of the multiplexer220 at the main divider circuitry 202. The plots 610, 612, and 614 showsignals at the first input S1 (output for the fifth latch 512), secondinput S2 (output for the sixth latch 514), and output, respectively, ofthe multiplexer 520 at the balance divider circuitry 502.

The multiplexer 220 from the main divider circuitry 202 and themultiplexer 520 from the balance divider circuitry 502 of FIG. 5 areshown on the left side of the FIG. 6 . As can be seen, the multiplexer520 from the balance divider circuitry 502 perform signal selection(e.g., between the first input S1 and the second input S2) responsive toopposite edges of the input signal 201 than the multiplexer 220 from themain divider circuitry 202. As an example, at time t1, the multiplexer220 switches from the second input S2 to the first input S1 based on arising edge of the input signal 201, whereas the multiplexer 520switches from the first input S1 to the second input S2 based on therising edge of the input signal 201. At time t2, the multiplexer 220switches from the first input S1 to the second input S2 based on afalling edge of the input signal 201, whereas the multiplexer 520switches from the second input S2 to the first input S1 based on thefalling edge of the input signal 201.

FIG. 7 is a schematic diagram illustrating exemplary duty cyclecorrection circuitry 700, according to embodiments of the presentdisclosure. In some aspects, the frequency synthesizer 100 of FIG. 1 mayinclude the duty cycle correction circuitry 700 as part of the frequencydivider circuitry 150. In some aspects, the duty cycle correctioncircuitry 420 of FIG. 4 may adjust or regulate the duty cycle (e.g., toa target duty cycle of 50%) of a frequency-divided signal using the dutycycle correction circuitry 700. As shown, the duty cycle correctioncircuitry 700 may include a DLL 701. The DLL 701 may include pulsegeneration circuitry 710, inverters 720, and duty cycle detectioncircuitry 730 in a forward path, and a variable delay line 740 in afeedback path.

In the illustrated example of FIG. 7 , the pulse generation circuitry710 may include a set-reset (SR) flip-flop 716 including a pair ofcross-coupled NAND gates 717 and 718, an inverter 712 coupled to aninput of the NAND gate 717 and another inverter 714 coupled to an inputof the NAND gate 718. The pulse generation circuitry 710 may receive afrequency-divide signal 702. The frequency-divide signal 702 may be afrequency-divided signal 702 output by a fractional divider circuitrysimilar to the fractional divider circuitry 200 or the frequency dividercircuitry 410. The frequency-divide signal 702 may be inverted by theinverter 712 and used to set and drive an output signal 704 to a logichigh state. A feedback signal 708 from the DLL 701 may be inverted bythe inverter 714 and used to reset and drive the output signal 704 to alogic low state. That is, the pulse generation circuitry 710 maygenerate the rising edges of the output signal 704 from the rising edgesof the frequency-divide signal 702 and generate the falling edges of theoutput signal 704 from the rising edges of the feedback signal 708. Thepulse generation circuitry 710 may be coupled to the inverters 720 todelay the output of the output signal 704 from the duty cycle correctioncircuitry 700. The delayed output signal at the output (e.g., at nodeN2) of the duty cycle correction circuitry 700 is shown by 706. WhileFIG. 7 illustrates two inverters 720 connected in series at the outputof the pulse generation circuitry 710, any suitable number of inverters720 may be arranged between the pulse generation circuitry 710 and theoutput of the duty cycle correction circuitry 700 depending on thedesired delay.

The duty cycle detection circuitry 730 is coupled to the output node N2.The duty cycle detection circuitry 730 may detect the duty cycle of theoutput signal 706 and guide the controlling of the variable delay line740 in the feedback path. As shown, the duty cycle detection circuitry730 may include a filter 732 and an error amplifier 738. The filter 732may be implemented as a lowpass filter coupled between the node N2 and aground potential (shown by the inverted triangle symbol). The filter 732may filter the output signal 706. In the illustrated example, the filter732 may include a resistor R 734 connected in series with a capacitor C736. The filter 732 may output a DC component of the output signal 706.The error amplifier 738 may include a first input coupled to a junctionor node between the resistor R 734 and the capacitor C 736, and a secondinput coupled to a reference voltage shown as Vref. The error amplifier738 may be a single-ended amplifier and may compare the DC component ofthe output signal 706 to the reference voltage and output an errorsignal 707 (e.g., a voltage difference between the DC component of theoutput signal 706 and the reference voltage). As discussed above, insome aspects, it may be desirable to have a frequency-divided signalwith a 50% duty cycle. To achieve a target duty cycle of 50%, thereference voltage may be set to about half of the supply voltage. Thatis, if the output signal 706 has a 50% duty cycle, the average (or DCcomponent) of the output signal 706 may be about half of the supplyvoltage, and hence the error signal 707 may be at zero Volt. If,however, there output signal 706 has a duty cycle lower than 50%, theaverage (or DC component) of the output signal 706 may be less than halfof the supply voltage, and hence the error signal 707 can be indicativeof the amount of a duty cycle error in the output signal 706. Forexample, the voltage level of the error signal 707 may be aboutproportional to a duty cycle error amount. As such, the error signal 707can be used to control the variable delay line 740.

The variable delay line 740 may include a plurality of delay elements742, for example, implemented as inverters as shown in the example. Thevariable delay line 740 may be coupled to the output of the lastinverter 720, for example, at node N3, which can be the same node as N2.The variable delay line 740 may delay the output signal 706 based on theerror signal 707 to provide the feedback signal 708. The variable delayline 740 may be a voltage-controlled delay line and may apply an amountof delay in response to the error voltage (the error signal 707) outputby the error amplifier 738. As discussed above, feedback signal 708 isused to reset and drive the output signal 704 to a logic low state. Thatis, the DLL 701 may adjust the delay of the feedback signal 708 untilthe output signal 704 or the output signal 706 is at the target dutycycle of 50%. Accordingly, the output signal 704 or 706 may be referredto as the duty cycle-adjusted frequency-divided signal.

Because the feedback signal 708 is generated based on circuitries at thefilter 732 and error amplifier 738 and the variable delay line 740, thefeedback signal 708 may have noise characteristics introduced by thosecircuitries. Further, because the falling edges of the output signal 704is generated from the feedback signal 708, the falling edges of theoutput signal 704 and the delayed output signal 706 can have noisecharacteristics from the variable delay line 740 and the duty cycledetection circuitry 730. Accordingly, the rising edges of the outputsignal 706 or the duty cycle-adjusted frequency-divided signal outputmay be clean (e.g., low noise) but the falling edges of the outputsignal 706 can be noisy. By having at least clean rising edges in theoutput signal 706, the duty cycle correction circuitry 700 may behelpful in some circuitries such as ADC circuitries (e.g., pipelineADCs) in which rising edges are used for sampling in sample and holdcircuitries and falling edges are used to transition between a samplingstage and a hold stage. The duty cycle correction techniques provided bythe duty cycle correction circuitry 700 may also allow for maximizingthe amplifier 738 settling time without much added jitter to the sampleddata. Accordingly, the duty cycle correction circuitry 700 may bebeneficial for use in providing clock signals to ADC circuitries.

In other aspects, the duty cycle detection circuitry 730 can beconfigured to meet a target duty cycle other than 50%. For instance, itmay be desirable to have a longer or wider clock pulse to allow for acertain circuit operation. For instance, the reference voltage at theerror amplifier 738 can be varied to change the duty cycle of the outputsignal 706, for example, by adding an offset to the reference voltage.Varying the duty cycle can allow for tradeoffs between sample time and amultiplying digital-to-analog converter (MDAC) settling in a pipelineADC, for example.

FIG. 8 is a timing diagram 800 illustrating signals in the duty cyclecorrection circuitry 700 of FIG. 7 , according to embodiments of thepresent disclosure. In FIG. 8 , the x-axis may represent time in somearbitrary units. The rising edges of the pulses are shown by up arrowsand the falling edges of the pulses are shown by down arrows. The plot802 illustrates the frequency-divided signal 702 at the input of theduty cycle correction circuitry 700. The plot 804 illustrates thefeedback signal 708 generated based on the duty cycle detectioncircuitry 730 and the variable delay line 740. The plot 806 illustratesthe output signal 706 (the duty cycle-adjusted signal) at the output ofthe duty cycle correction circuitry 700. As shown by the dotted arrows,a rising edge of the output signal 706 is generated from a rising edgeof the frequency-divided signal 702 while a falling edge of the outputsignal 706 is generated from a rising edge of the feedback signal 708.As can be seen from FIG. 8 , the frequency-divided signal 702 at theinput of the duty cycle correction circuitry 700 has a duty cycle ofabout 33%, and the output signal 706 at the output of the duty cyclecorrection circuitry 700 is regulated to have a duty cycle of about 50%.

FIG. 9 is a schematic diagram illustrating exemplary duty cyclecorrection circuitry 900, according to embodiments of the presentdisclosure. In some aspects, the frequency synthesizer 100 of FIG. 1 mayinclude the duty cycle correction circuitry 900 as part of the frequencydivider circuitry 150. In some aspects, the duty cycle correctioncircuitry 420 of FIG. 4 may adjust or regulate the duty cycle (e.g., toa target duty cycle of 50%) of a frequency-divided signal using the dutycycle correction circuitry 900. The duty cycle correction circuitry 900may share many elements with the duty cycle correction circuitry 700 ofFIG. 7 ; for brevity, a discussion of these elements is not repeated,and these elements may take the form of any of the embodiments disclosedherein. As shown in FIG. 9 , the duty cycle correction circuitry 900 mayinclude a DLL 901. The DLL 901 may include pulse generation circuitry910, inverters 920, and duty cycle detection circuitry 730 in a forwardpath, and a variable delay line 740 in a feedback path.

In the illustrated example of FIG. 9 , the pulse generation circuitry910 may include a 2-input NAND gate 914, an inverter 912 coupled to aninput of the NAND gate 914 and another inverter 916 coupled to the otherinput of the NAND gate 914. The pulse generation circuitry 910 mayreceive a frequency-divide signal 902. The frequency-divide signal 902may be a frequency-divided signal 702 output by a fractional dividercircuitry similar to the fractional divider circuitry 200 or thefrequency divider circuitry 410. The frequency-divide signal 902 may beinverted by the inverter 912 and used to drive an output signal 904 (atthe output of the NAND gate 914) to a logic high state. A feedbacksignal 908 may be inverted by the inverter 916 and used to gate or delaythe resetting of the output signal 904 to a logic low state. That is,the pulse generation circuitry 910 may operate to extend the pulses ofthe frequency-divided signal 902 by generating the rising edges of theoutput signal 904 from rising edges of the frequency-divide signal 902and generating the falling edges of the output signal 904 from a delayedversion of the falling edges of the frequency-divided signal 902.

Similar to the duty cycle correction circuitry 700, the pulse generationcircuitry 910 may be coupled to the inverters 920 to delay the output ofthe output signal 904 from the duty cycle correction circuitry 900. Thedelayed output signal at the output (e.g., at node N4) of the duty cyclecorrection circuitry 900 is shown by 906. While FIG. 9 illustrates twoinverters 920 at the output of the pulse generation circuitry 910, anysuitable number of inverters 920 may be arranged between the pulsegeneration circuitry 910 and the output of the duty cycle correctioncircuitry 900 depending on the desired delay. Further, the duty cycledetection circuitry 730 is coupled to the output node N3 may operate asdiscussed above with reference to FIG. 7 . The duty cycle detectioncircuitry 730 may provide an error signal 907 based on a comparisonbetween a DC component or a signal average of the output signal 906 andthe reference voltage Vref. The error signal 907 may be a voltagedifference between the DC component of the output signal 906 and thereference voltage Vref and may be used to control the variable delayline 740.

The variable delay line 740 may be coupled to the input of the dutycycle correction circuitry 900 to receive the frequency-divided signal902. The variable delay line 740 may generate the feedback signal 908 togate or delay the falling edges of the frequency-divided signal 902based on the error signal 907 (which indicates a deviation of the dutycycle of the output signal 906 from a target duty cycle of 50%). Thatis, the DLL 901 may adjust the delay of the feedback signal 908 untilthe output signal 904 or the output signal 906 is at the target dutycycle of 50%. Accordingly, the output signal 904 or 906 may be referredto as the duty cycle-adjusted frequency-divided signal. In some aspects,a voltage offset can be added to the error amplifier 738 to achieve acertain desired duty cycle (e.g., greater than or less than 50%).

Similar to the duty cycle correction circuitry 700, because the feedbacksignal 908 is generated based on circuitries at the filter 732 and erroramplifier 738 and the variable delay line 740, the feedback signal 908may have noise characteristics introduced by those circuitries. Further,because the falling edges of the output signal 904 is generated from thefeedback signal 908, the falling edges of the output signal 904 and thedelayed output signal 906 can have noise characteristics from thevariable delay line 740 and the duty cycle detection circuitry 730. Assuch, by having at least clean rising edges in the output signal 906,the duty cycle correction circuitry 900 may be helpful in somecircuitries such as ADC circuitries in which rising edges may be usedfor triggering certain operations and falling edges may be used fortransitioning between operational states as discussed above withreference to FIG. 7 .

FIG. 10 is a timing diagram 1000 illustrating signals in the duty cyclecorrection circuitry 900 of FIG. 9 , according to embodiments of thepresent disclosure. In FIG. 10 , the x-axis may represent time in somearbitrary units. The rising edges of the pulses are shown by up arrowsand the falling edges of the pulses are shown by down arrows. The plot1002 illustrates the frequency-divided signal 902 at the input of theduty cycle correction circuitry 900. The plot 1004 illustrates thefeedback signal 908 generated based on the duty cycle detectioncircuitry 730 and the variable delay line 740. The plot 1006 illustratesthe output signal 906 (the duty cycle-adjusted signal) at the output ofthe duty cycle correction circuitry 900. As shown by the dotted arrows,a rising edge of the output signal 906 is generated from a rising edgeof the frequency-divided signal 902 while a falling edge of the outputsignal 906 is generated by delaying a falling edge of thefrequency-divided signal 902 by a delay 1008, which is responsive to arising edge of the feedback signal 908. As can be seen from FIG. 10 ,the frequency-divided signal 902 at the input of the duty cyclecorrection circuitry 900 has a duty cycle of about 33%, and the outputsignal 906 at the output of the duty cycle correction circuitry 900 isregulated to have a duty cycle of about 50%.

While FIG. 7 illustrates the duty cycle correction circuitry 700utilizing an SR flip-flop 716 for pulse generation and FIG. 9illustrates the duty cycle correction circuitry 900 utilizing a NANDgate 914 for pulse generation, other implementations of pulse generationcircuitry can be used in a DLL for duty cycle correction or regulation.

Example RF Device

FIG. 11 is block diagram illustrating an exemplary RF device 2200, e.g.,an RF transceiver, in which one or more duty cycle regulated, balancedfractional dividers as disclosed herein may be implemented, according toembodiments of the present disclosure.

In general, the RF device 2200 may be any device or system that maysupport wireless transmission and/or reception of signals in the form ofelectromagnetic waves in the RF range of approximately 3 kilohertz (kHz)to approximately 300 Gigahertz (GHz). In some embodiments, the RF device2200 may be used for wireless communications, e.g., in a base station(BS) or a UE device of any suitable cellular wireless communicationstechnology, such as GSM, WCDMA, or LTE. In a further example, the RFdevice 2200 may be used as, or in, e.g., a BS or a UE device of amillimeter-wave wireless technology such as fifth generation (5G)wireless (i.e., high-frequency/short wavelength spectrum, e.g., withfrequencies in the range between about 20 and 60 GHz, corresponding towavelengths in the range between about 5 and 15 millimeters). In yetanother example, the RF device 2200 may be used for wirelesscommunications using Wi-Fi technology (e.g., a frequency band of 2.4GHz, corresponding to a wavelength of about 12 cm, or a frequency bandof 5.8 GHz, spectrum, corresponding to a wavelength of about 5 cm),e.g., in a Wi-Fi-enabled device such as a desktop, a laptop, a videogame console, a smart phone, a tablet, a smart TV, a digital audioplayer, a car, a printer, etc. In some implementations, a Wi-Fi-enableddevice may, e.g., be a node in a smart system configured to communicatedata with other nodes, e.g., a smart sensor. Still in another example,the RF device 2200 may be used for wireless communications usingBluetooth technology (e.g., a frequency band from about 2.4 to about2.485 GHz, corresponding to a wavelength of about 12 cm). In otherembodiments, the RF device 2200 may be used for transmitting and/orreceiving RF signals for purposes other than communication, e.g., in anautomotive radar system, or in medical applications such asmagneto-resonance imaging (MRI).

In various embodiments, the RF device 2200 may be included infrequency-division duplex (FDD) or time-domain duplex (TDD) variants offrequency allocations that may be used in a cellular network. In an FDDsystem, the uplink (i.e., RF signals transmitted from the UE devices toa BS) and the downlink (i.e., RF signals transmitted from the BS to theUS devices) may use separate frequency bands at the same time. In a TDDsystem, the uplink and the downlink may use the same frequencies but atdifferent times.

Several components are illustrated in FIG. 11 as included in the RFdevice 2200, but any one or more of these components may be omitted orduplicated, as suitable for the application. For example, in someembodiments, the RF device 2200 may be an RF device supporting both ofwireless transmission and reception of RF signals (e.g., an RFtransceiver), in which case it may include both the components of whatis referred to herein as a transmit (TX) path and the components of whatis referred to herein as a receive (RX) path. However, in otherembodiments, the RF device 2200 may be an RF device supporting onlywireless reception (e.g., an RF receiver), in which case it may includethe components of the RX path, but not the components of the TX path; orthe RF device 2200 may be an RF device supporting only wirelesstransmission (e.g., an RF transmitter), in which case it may include thecomponents of the TX path, but not the components of the RX path.

In some embodiments, some or all the components included in the RFdevice 2200 may be attached to one or more motherboards. In someembodiments, some or all these components are fabricated on a singledie, e.g., on a single system on chip (SoC) die.

Additionally, in various embodiments, the RF device 2200 may not includeone or more of the components illustrated in FIG. 11 , but the RF device2200 may include interface circuitry for coupling to the one or morecomponents. For example, the RF device 2200 may not include an antenna2202, but may include antenna interface circuitry (e.g., a matchingcircuitry, a connector and driver circuitry) to which an antenna 2202may be coupled. In another set of examples, the RF device 2200 may notinclude a digital processing unit 2208 or a local oscillator 2206, butmay include device interface circuitry (e.g., connectors and supportingcircuitry) to which a digital processing unit 2208 or a local oscillator2206 may be coupled.

As shown in FIG. 11 , the RF device 2200 may include an antenna 2202, aduplexer 2204 (e.g., if the RF device 2200 is an FDD RF device;otherwise the duplexer 2204 may be omitted), a local oscillator 2206, adigital processing unit 2208. As also shown in FIG. 11 , the RF device2200 may include an RX path that may include an RX path amplifier 2212,an RX path pre-mix filter 2214, a RX path mixer 2216, an RX pathpost-mix filter 2218, and an analog-to-digital converter (ADC) 2220. Asfurther shown in FIG. 11 , the RF device 2200 may include a TX path thatmay include a TX path amplifier 2222, a TX path post-mix filter 2224, aTX path mixer 2226, a TX path pre-mix filter 2228, and adigital-to-analog converter (DAC) 2230. Still further, the RF device2200 may further include an impedance tuner 2232, an RF switch 2234, andcontrol logic 2236. In various embodiments, the RF device 2200 mayinclude multiple instances of any of the components shown in FIG. 11 .In some embodiments, the RX path amplifier 2212, the TX path amplifier2222, the duplexer 2204, and the RF switch 2234 may be considered toform, or be a part of, an RF front-end (FE) of the RF device 2200. Insome embodiments, the RX path amplifier 2212, the TX path amplifier2222, the duplexer 2204, and the RF switch 2234 may be considered toform, or be a part of, an RF FE of the RF device 2200. In someembodiments, the RX path mixer 2216 and the TX path mixer 2226 (possiblywith their associated pre-mix and post-mix filters shown in FIG. 11 )may be considered to form, or be a part of, an RF transceiver of the RFdevice 2200 (or of an RF receiver or an RF transmitter if only RX pathor TX path components, respectively, are included in the RF device2200). In some embodiments, the RF device 2200 may further include oneor more control logic elements/circuits, shown in FIG. 11 as controllogic 2236, e.g., an RF FE control interface. In some embodiments, thecontrol logic 2236 may be used to control other functions within the RFdevice 2200, e.g., enhance control of complex RF system environment,support implementation of envelope tracking techniques, reducedissipated power, etc.

The antenna 2202 may be configured to wirelessly transmit and/or receiveRF signals in accordance with any wireless standards or protocols, e.g.,Wi-Fi, LTE, or GSM, as well as any other wireless protocols that aredesignated as 3G, 4G, 5G, and beyond. If the RF device 2200 is an FDDtransceiver, the antenna 2202 may be configured for concurrent receptionand transmission of communication signals in separate, i.e.,non-overlapping and non-continuous, bands of frequencies, e.g., in bandshaving a separation of, e.g., 20 MHz from one another. If the RF device2200 is a TDD transceiver, the antenna 2202 may be configured forsequential reception and transmission of communication signals in bandsof frequencies that may be the same or overlapping for TX and RX paths.In some embodiments, the RF device 2200 may be a multi-band RF device,in which case the antenna 2202 may be configured for concurrentreception of signals having multiple RF components in separate frequencybands and/or configured for concurrent transmission of signals havingmultiple RF components in separate frequency bands. In such embodiments,the antenna 2202 may be a single wide-band antenna or a plurality ofband-specific antennas (i.e., a plurality of antennas each configured toreceive and/or transmit signals in a specific band of frequencies). Invarious embodiments, the antenna 2202 may include a plurality of antennaelements, e.g., a plurality of antenna elements forming a phased antennaarray (i.e., a communication system or an array of antennas that may usea plurality of antenna elements and phase shifting to transmit andreceive RF signals). Compared to a single-antenna system, a phasedantenna array may offer advantages such as increased gain, ability ofdirectional steering, and simultaneous communication. In someembodiments, the RF device 2200 may include more than one antenna 2202to implement antenna diversity. In some such embodiments, the RF switch2234 may be deployed to switch between different antennas.

An output of the antenna 2202 may be coupled to the input of theduplexer 2204. The duplexer 2204 may be any suitable componentconfigured for filtering multiple signals to allow for bidirectionalcommunication over a single path between the duplexer 2204 and theantenna 2202. The duplexer 2204 may be configured for providing RXsignals to the RX path of the RF device 2200 and for receiving TXsignals from the TX path of the RF device 2200.

The RF device 2200 may include one or more local oscillators 2206,configured to provide local oscillator signals that may be used fordownconversion of the RF signals received by the antenna 2202 and/orupconversion of the signals to be transmitted by the antenna 2202.

The RF device 2200 may include the digital processing unit 2208, whichmay include one or more processing devices. The digital processing unit2208 may be configured to perform various functions related to digitalprocessing of the RX and/or TX signals. Examples of such functionsinclude, but are not limited to, decimation/downsampling, errorcorrection, digital downconversion or upconversion, DC offsetcancellation, automatic gain control, etc. Although not shown in FIG. 11, in some embodiments, the RF device 2200 may further include a memorydevice, configured to cooperate with the digital processing unit 2208.

Turning to the details of the RX path that may be included in the RFdevice 2200, the RX path amplifier 2212 may include a low-noiseamplifier (LNA). An input of the RX path amplifier 2212 may be coupledto an antenna port (not shown) of the antenna 2202, e.g., via theduplexer 2204. The RX path amplifier 2212 may amplify the RF signalsreceived by the antenna 2202.

An output of the RX path amplifier 2212 may be coupled to an input ofthe RX path pre-mix filter 2214, which may be a harmonic or band-pass(e.g., low-pass) filter, configured to filter received RF signals thathave been amplified by the RX path amplifier 2212.

An output of the RX path pre-mix filter 2214 may be coupled to an inputof the RX path mixer 2216, also referred to as a downconverter. The RXpath mixer 2216 may include two inputs and one output. A first input maybe configured to receive the RX signals, which may be current signals,indicative of the signals received by the antenna 2202 (e.g., the firstinput may receive the output of the RX path pre-mix filter 2214). Asecond input may be configured to receive local oscillator signals fromone of the local oscillators 2206. The RX path mixer 2216 may then mixthe signals received at its two inputs to generate a downconverted RXsignal, provided at an output of the RX path mixer 2216. As used herein,downconversion refers to a process of mixing a received RF signal with alocal oscillator signal to generate a signal of a lower frequency. Inparticular, the TX path mixer (e.g., downconverter) 2216 may beconfigured to generate the sum and/or the difference frequency at theoutput port when two input frequencies are provided at the two inputports. In some embodiments, the RF device 2200 may implement adirect-conversion receiver (DCR), also known as homodyne, synchrodyne,or zero-IF receiver, in which case the RX path mixer 2216 may beconfigured to demodulate the incoming radio signals using localoscillator signals whose frequency is identical to, or very close to thecarrier frequency of the radio signal. In other embodiments, the RFdevice 2200 may make use of downconversion to an intermediate frequency(IF). IFs may be used in superheterodyne radio receivers, in which areceived RF signal is shifted to an IF before the final detection of theinformation in the received signal is done. Conversion to an IF may beuseful for several reasons. For example, when several stages of filtersare used, they can all be set to a fixed frequency, which makes themeasier to build and to tune. In some embodiments, the RX path mixer 2216may include several such stages of IF conversion.

Although a single RX path mixer 2216 is shown in the RX path of FIG. 11, in some embodiments, the RX path mixer 2216 may be implemented as aquadrature downconverter, in which case it would include a first RX pathmixer and a second RX path mixer. The first RX path mixer may beconfigured for performing downconversion to generate an in-phase (I)downconverted RX signal by mixing the RX signal received by the antenna2202 and an in-phase component of the local oscillator signal providedby the local oscillator 2206. The second RX path mixer may be configuredfor performing downconversion to generate a quadrature (Q) downconvertedRX signal by mixing the RX signal received by the antenna 2202 and aquadrature component of the local oscillator signal provided by thelocal oscillator 2206 (the quadrature component is a component that isoffset, in phase, from the in-phase component of the local oscillatorsignal by 90 degrees). The output of the first RX path mixer may beprovided to a I-signal path, and the output of the second RX path mixermay be provided to a Q-signal path, which may be substantially 90degrees out of phase with the I-signal path.

The output of the RX path mixer 2216 may, optionally, be coupled to theRX path post-mix filter 2218, which may be low-pass filters. In case theRX path mixer 2216 is a quadrature mixer that implements the first andsecond mixers as described above, the in-phase and quadrature componentsprovided at the outputs of the first and second mixers respectively maybe coupled to respective individual first and second RX path post-mixfilters included in the filter 2218.

The ADC 2220 may be configured to convert the mixed RX signals from theRX path mixer 2216 from analog to digital domain. The ADC 2220 may be aquadrature ADC that, like the RX path quadrature mixer 2216, may includetwo ADCs, configured to digitize the downconverted RX path signalsseparated in in-phase and quadrature components. The output of the ADC2220 may be provided to the digital processing unit 2208, configured toperform various functions related to digital processing of the RXsignals so that information encoded in the RX signals can be extracted.

Turning to the details of the TX path that may be included in the RFdevice 2200, the digital signal to later be transmitted (TX signal) bythe antenna 2202 may be provided, from the digital processing unit 2208,to the DAC 2230. Like the ADC 2220, the DAC 2230 may include two DACs,configured to convert, respectively, digital I- and Q-path TX signalcomponents to analog form.

Optionally, the output of the DAC 2230 may be coupled to the TX pathpre-mix filter 2228, which may be a band-pass (e.g., low-pass) filter(or a pair of band-pass, e.g., low-pass, filters, in case of quadratureprocessing) configured to filter out, from the analog TX signals outputby the DAC 2230, the signal components outside of the desired band. Thedigital TX signals may then be provided to the TX path mixer 2226, whichmay also be referred to as an upconverter. Like the RX path mixer 2216,the TX path mixer 2226 may include a pair of TX path mixers, forin-phase and quadrature component mixing. Like the first and second RXpath mixers that may be included in the RX path, each of the TX pathmixers of the TX path mixer 2226 may include two inputs and one output.A first input may receive the TX signal components, converted to theanalog form by the respective DAC 2230, which are to be upconverted togenerate RF signals to be transmitted. The first TX path mixer maygenerate an in-phase (I) upconverted signal by mixing the TX signalcomponent converted to analog form by the DAC 2230 with the in-phasecomponent of the TX path local oscillator signal provided from the localoscillator 2206 (in various embodiments, the local oscillator 2206 mayinclude a plurality of different local oscillators, or be configured toprovide different local oscillator frequencies for the mixer 2216 in theRX path and the mixer 2226 in the TX path). The second TX path mixer maygenerate a quadrature phase (Q) upconverted signal by mixing the TXsignal component converted to analog form by the DAC 2230 with thequadrature component of the TX path local oscillator signal. The outputof the second TX path mixer may be added to the output of the first TXpath mixer to create a real RF signal. A second input of each of the TXpath mixers may be coupled the local oscillator 2206.

Optionally, the RF device 2200 may include the TX path post-mix filter2224, configured to filter the output of the TX path mixer 2226.

In various embodiments, any of the RX path pre-mix filter 2214, the RXpath post-mix filter 2218, the TX post-mix filter 2224, and the TXpre-mix filter 2228 may be implemented as RF filters. In someembodiments, an RF filter may be implemented as a plurality of RFfilters, or a filter bank. A filter bank may include a plurality of RFfilters that may be coupled to a switch, e. g., the RF switch 2234,configured to selectively switch any one of the plurality of RF filterson and off (e.g., activate any one of the plurality of RF filters), inorder to achieve desired filtering characteristics of the filter bank(i.e., in order to program the filter bank). For example, such a filterbank may be used to switch between different RF frequency ranges whenthe RF device 2200 is, or is included in, a BS or in a UE device. Inanother example, such a filter bank may be programmable to suppress TXleakage on the different duplex distances.

The impedance tuner 2232 may include any suitable circuitry, configuredto match the input and output impedances of the different RF circuitriesto minimize signal losses in the RF device 2200. For example, theimpedance tuner 2232 may include an antenna impedance tuner. Being ableto tune the impedance of the antenna 2202 may be particularlyadvantageous because antenna's impedance is a function of theenvironment that the RF device 2200 is in, e.g., antenna's impedancechanges depending on, e.g., if the antenna is held in a hand, placed ona car roof, etc.

As described above, the RF switch 2234 may be a device configured toroute high-frequency signals through transmission paths, e.g., in orderto selectively switch between a plurality of instances of any one of thecomponents shown in FIG. 11 , e.g., to achieve desired behavior andcharacteristics of the RF device 2200. For example, in some embodiments,an RF switch may be used to switch between different antennas 2202. Inother embodiments, an RF switch may be used to switch between aplurality of RF filters (e.g., by selectively switching RF filters onand off) of the RF device 2200. Typically, an RF system would include aplurality of such RF switches.

The RF device 2200 provides a simplified version and, in furtherembodiments, other components not specifically shown in FIG. 11 may beincluded. For example, the RX path of the RF device 2200 may include acurrent-to-voltage amplifier between the RX path mixer 2216 and the ADC2220, which may be configured to amplify and convert the downconvertedsignals to voltage signals. In another example, the RX path of the RFdevice 2200 may include a balun transformer for generating balancedsignals. In yet another example, the RF device 2200 may further includea clock generator, which may, e.g., include a suitable phased-lock loop(PLL), configured to receive a reference clock signal and use it togenerate a different clock signal that may then be used for timing theoperation of the ADC 2220, the DAC 2230, and/or that may also be used bythe local oscillator 2206 to generate the local oscillator signals to beused in the RX path or the TX path. In general, RF device 2200 mayinclude clock generation circuitries or PLL in various domains such asin a RF domain, a digital I/O domain (e.g., for communications withdevices outside of the RF device), clock domain, etc. In someembodiments, the clock generator or PLL may be similar to the frequencysynthesizer 100 discussed above with reference to FIG. 1 . In someembodiments, the clock generator or PLL may utilize fractional frequencydividers similar to the duty cycle-regulated, balanced fractionalfrequency divider circuitry 400 discussed above with reference to FIGS.4-9 to provide clock signals with a low subharmonic distortion and a 50%duty cycle.

Examples

In Example 1 includes an apparatus including frequency divider circuitryincluding a first node to receive an input signal; fractional dividercircuitry to generate, based on the input signal and afrequency-division ratio, a first signal having a first series of pulseswith adjacent pulses triggered by opposite edges of the input signal,where the fractional divider circuitry includes first signal selectioncircuitry; balancer divider circuitry to generate, based on the inputsignal, a second signal having a second series of pulses aligned to thefirst series of pulses, where the balancer divider circuitry includessecond signal selection circuitry triggered by opposite edges of theinput signal than the first signal selection circuitry; and a secondnode to combine the first signal and the second signal.

In Example 2, the apparatus of Example 1 can optionally include thebalancer divider circuitry generates the second signal using the samefrequency-division ratio as the fractional divider circuitry.

In Example 3, the apparatus of any of Examples 1-2 can optionallyinclude the frequency-division ratio is 1.5.

In Example 4, the apparatus of any of Examples 1-3 can optionallyinclude each of the first signal selection circuitry and the secondsignal selection circuitry has a respective first input, a respectivesecond input, and a respective output; the first signal selectioncircuitry switches from selecting the first respective input toselecting the second respective input responsive to one of a firstrising edge or a first falling edge of the input signal; and the secondsignal selection circuitry switches from selecting the respective firstinput to selecting the respective second input responsive to the otherone of the first rising edge or the first falling edge of the inputsignal.

In Example 5, the apparatus of any of Examples 1-4 can optionallyinclude the first signal selection circuitry and the second signalselection circuitry have the same circuit topology.

In Example 6, the apparatus of any of Examples 1-5 can optionallyinclude the fractional divider circuitry further includes first dualedge-triggered circuitry to generate a third signal and a fourth signalresponsive respectively to the first falling edge and the first risingedge of the input signal, third signal and the fourth signal receivedrespectively at the respective first input and the respective secondinput of the first signal selection circuitry; and the balancer dividercircuitry further includes second dual edge-triggered circuitry togenerate a fifth signal and a sixth signal responsive respectively tothe first rising edge and the first falling edge of the input signal,the fifth signal and the sixth signal received respectively at therespective first input and the respective second input of the secondsignal selection circuitry.

In Example 7, the apparatus of any of Examples 1-6 can optionallyinclude the fractional divider circuitry further includes feedbackcircuitry to generate a feedback signal based on the combined firstsignal and second signal; the fractional divider circuitry generates thefirst signal further based on the feedback signal; and the balancerdivider circuitry generates the second signal further based on thefeedback signal.

In Example 8, the apparatus of any of Examples 1-7 can optionallyinclude the frequency divider circuitry further includes duty cyclecorrection circuitry to adjust a duty cycle of the combined first signaland second signal based on a feedback indicative of duty information ofthe combined first signal and second signal and a target duty cycle.

In Example 9, the apparatus of any of Examples 1-8 can optionallyinclude a phased-locked loop (PLL) including a voltage-controlledoscillator (VCO) to output a VCO signal; and the frequency dividercircuitry coupled to the VCO, where the input signal corresponds to theVCO output signal.

In Example 10, the apparatus of any of Examples 1-9 can optionallyinclude the PLL further includes third signal selection circuitry toselect between the VCO output signal or an output signal of thefrequency divider circuitry.

In Example 11, the apparatus of any of Examples 1-10 can optionallyinclude the apparatus is a radio transceiver integrated circuit.

Example 12 includes an apparatus including frequency divider circuitryincluding an input node to receive an input signal; fractional dividercircuitry to generate a frequency-divided signal from the input signal,where adjacent pulses in the frequency-divided signal are triggered byopposite edges of the input signal; and duty cycle correctiondelay-locked loop (DLL) to adjust a duty cycle of the frequency-dividedsignal.

In Example 13, the apparatus of Example 12 can optionally include theduty cycle DLL generates a rising edge of a duty cycle-adjusted signalfrom a rising edge of the frequency-divided signal; and generates afalling edge of the duty cycle-adjusted signal based on an error signalindicative of duty cycle information of the frequency-divided signal.

In Example 14, the apparatus of any of Examples 12-13 can optionallyinclude the duty cycle DLL includes a filter to output a direct current(DC) component of the frequency-divided signal; and an amplifier havinga first input to receive the DC component of the frequency-dividedsignal; a second input to receive a reference voltage; and an output tooutput the error signal; and a variable delay line controlled by theerror signal to generate a feedback signal.

In Example 15, the apparatus of any of Examples 12-14 can optionallyinclude the reference voltage at the second input of the amplifier ishalf of a supply voltage.

In Example 16, the apparatus of any of Examples 12-15 can optionallyinclude the reference voltage at the second input of the amplifier isconfigured based on the target duty cycle.

In Example 17, the apparatus of any of Examples 12-16 can optionallyinclude the duty cycle correction DLL generates the falling edge of theduty cycle-adjusted signal further from a rising edge of the feedbacksignal.

In Example 18, the apparatus of any of Examples 12-16 can optionallyinclude the duty cycle DLL generates the falling edge of the dutycycle-adjusted signal further by gating a falling edge of thefrequency-divided signal by the feedback signal.

In Example 19, the apparatus of any of Examples 12-18 can optionallyinclude balancer divider circuitry to generate a first signal having asame phase as the frequency-divided signal, where the balancer dividercircuitry includes a first multiplexer that is triggered by oppositeedges of the input signal than a second multiplexer in the fractionaldivider circuitry; and a summing node to add the first signal to thefrequency-divided signal.

In Example 20, the apparatus of any of Examples 12-19 can optionallyinclude a phase-locked loop (PLL) including a voltage-controlledoscillator (VCO); and the frequency divider circuitry coupled to theVCO.

In Example 21, the apparatus of any of Examples 12-20 can optionallyinclude integer divider circuitry to divide the duty cycle-adjustedsignal by a power of 2.

In Example 22, the apparatus of any of Examples 12-21 can optionallyinclude the apparatus is a radio transceiver integrated circuit.

Example 23 includes an integrated circuit device including frequencysynthesizer circuitry including a voltage-controlled oscillator (VCO) togenerate a reference clock signal; frequency divider circuitry to dividea frequency of the reference clock signal by a fractional division ratioto generate a first signal; and subharmonic cancellation circuitry togenerate a second signal having the same phase as the first signal; andcombine the first signal and the second signal to generate a thirdsignal having a reduced sub-harmonic than the first signal, where thesubharmonic cancellation circuitry includes a replica circuitreplicating a first circuit of the frequency divider circuitry, wherethe replica circuit is triggered by opposite edges of the referenceclock signal than the first circuit; and duty cycle correction circuitryto adjust a duty cycle of the third signal to generate a dutycycle-corrected signal.

In Example 24, the integrated circuit device of Example 23 canoptionally include the first circuit of the frequency divider circuitryincludes a first multiplexer; the replica circuit of the subharmoniccancellation circuitry includes a second multiplexer; each of the firstmultiplexer and the second multiplexer has a respective first input, arespective second input, and a respective output; the first multiplexerswitches from selecting the first respective input to selecting thesecond respective input responsive to one of a rising edge or a fallingedge of the reference clock signal; and the second multiplexer switchesfrom selecting the respective first input to selecting the respectivesecond input responsive to the other one of the rising edge or thefalling edge of the reference clock signal.

In Example 25, the integrated circuit device of any of Examples 23-24can optionally include the duty cycle correction circuitry adjusts theduty cycle of the third signal by generating a rising edge of the dutycycle-corrected signal from a rising edge of the third signal;generating a falling edge the duty cycle-corrected signal from a risingedge of a feedback signal; and generating the feedback signal bydelaying the third signal by a delay associated with a duty cycle of thethird signal.

In Example 26, the integrated circuit device of any of Examples 23-24can optionally include the duty cycle correction circuitry adjusts theduty cycle of the third signal by generating a rising edge of the dutycycle-corrected signal from a rising edge of the third signal;generating a falling edge the duty cycle-corrected signal by gating afalling edge of the third signal by a rising edge of a feedback signal;and generating the feedback signal by delaying the third signal by adelay associated with a duty cycle of the third signal.

In Example 27, the integrated circuit device of any of Examples 23-27can optionally include radio frequency (RF) circuitry to generate an RFsignal based on the third signal.

In Example 28, the integrated circuit device of claim 23 can optionallyinclude analog-to-digital conversion (ADC) circuitry to sample a signalbased on the third signal.

In Example 29, the integrated circuit device of any of Examples 23-28can optionally include digital input/output (IO) circuitry to generate adigital signal based on the duty cycle-corrected signal.

VARIATIONS AND IMPLEMENTATIONS

While embodiments of the present disclosure were described above withreferences to exemplary implementations as shown in FIGS. 1-10 , aperson skilled in the art will realize that the various teachingsdescribed above are applicable to a large variety of otherimplementations.

In certain contexts, the features discussed herein can be applicable toautomotive systems, safety-critical industrial applications, medicalsystems, scientific instrumentation, wireless and wired communications,radio, radar, industrial process control, audio and video equipment,current sensing, instrumentation (which can be highly precise), andother digital-processing-based systems.

In the discussions of the embodiments above, components of a system,such as filters, converters, mixers, amplifiers, digital logiccircuitries, and/or other components can readily be replaced,substituted, or otherwise modified in order to accommodate particularcircuitry needs. Moreover, it should be noted that the use ofcomplementary electronic devices, hardware, software, etc., offer anequally viable option for implementing the teachings of the presentdisclosure related to fractional frequency dividers, in variouscommunication systems.

Parts of various systems for implementing duty cycle-regulated, balancedfractional frequency divider as proposed herein can include electroniccircuitry to perform the functions described herein. In some cases, oneor more parts of the system can be provided by a processor speciallyconfigured for carrying out the functions described herein. Forinstance, the processor may include one or more application specificcomponents, or may include programmable logic gates which are configuredto carry out the functions describe herein. The circuitry can operate inanalog domain, digital domain, or in a mixed-signal domain. In someinstances, the processor may be configured to carrying out the functionsdescribed herein by executing one or more instructions stored on anon-transitory computer-readable storage medium.

In one example embodiment, any number of electrical circuits of thepresent figures may be implemented on a board of an associatedelectronic device. The board can be a general circuit board that canhold various components of the internal electronic system of theelectronic device and, further, provide connectors for otherperipherals. More specifically, the board can provide the electricalconnections by which the other components of the system can communicateelectrically. Any suitable processors (inclusive of DSPs,microprocessors, supporting chipsets, etc.), computer-readablenon-transitory memory elements, etc. can be suitably coupled to theboard based on particular configuration needs, processing demands,computer designs, etc. Other components such as external storage,additional sensors, controllers for audio/video display, and peripheraldevices may be attached to the board as plug-in cards, via cables, orintegrated into the board itself. In various embodiments, thefunctionalities described herein may be implemented in emulation form assoftware or firmware running within one or more configurable (e.g.,programmable) elements arranged in a structure that supports thesefunctions. The software or firmware providing the emulation may beprovided on non-transitory computer-readable storage medium comprisinginstructions to allow a processor to carry out those functionalities.

In another example embodiment, the electrical circuits of the presentfigures may be implemented as stand-alone modules (e.g., a device withassociated components and circuitry configured to perform a specificapplication or function) or implemented as plug-in modules intoapplication specific hardware of electronic devices. Note thatparticular embodiments of the present disclosure may be readily includedin a system on chip (SOC) package, either in part, or in whole. An SOCrepresents an IC that integrates components of a computer or otherelectronic system into a single chip. It may contain digital, analog,mixed-signal, and often RF functions: all of which may be provided on asingle chip substrate. Other embodiments may include a multi-chip-module(MCM), with a plurality of separate ICs located within a singleelectronic package and configured to interact closely with each otherthrough the electronic package.

It is also imperative to note that all of the specifications,dimensions, and relationships outlined herein (e.g., the number ofcomponents of the apparatuses and/or RF device shown in FIGS. 1-2, 4-5,7, and 9-10 ) have only been offered for purposes of example andteaching only. Such information may be varied considerably withoutdeparting from the spirit of the present disclosure, or the scope of theappended claims. It should be appreciated that the system can beconsolidated in any suitable manner. Along similar design alternatives,any of the illustrated circuits, components, modules, and elements ofthe present figures may be combined in various possible configurations,all of which are clearly within the broad scope of this specification.In the foregoing description, example embodiments have been describedwith reference to particular processor and/or component arrangements.Various modifications and changes may be made to such embodimentswithout departing from the scope of the appended claims. The descriptionand drawings are, accordingly, to be regarded in an illustrative ratherthan in a restrictive sense.

Note that with the numerous examples provided herein, interaction may bedescribed in terms of two, three, four, or more electrical components.However, this has been done for purposes of clarity and example only. Itshould be appreciated that the system can be consolidated in anysuitable manner. Along similar design alternatives, any of theillustrated components, modules, and elements of the FIGURES may becombined in various possible configurations, all of which are clearlywithin the broad scope of this Specification. In certain cases, it maybe easier to describe one or more of the functionalities of a given setof flows by only referencing a limited number of electrical elements. Itshould be appreciated that the electrical circuits of the FIGURES andits teachings are readily scalable and can accommodate a large number ofcomponents, as well as more complicated/sophisticated arrangements andconfigurations. Accordingly, the examples provided should not limit thescope or inhibit the broad teachings of the electrical circuits aspotentially applied to a myriad of other architectures.

Note that in this Specification, references to various features (e.g.,elements, structures, modules, components, steps, operations,characteristics, etc.) included in “one embodiment”, “exampleembodiment”, “an embodiment”, “another embodiment”, “some embodiments”,“various embodiments”, “other embodiments”, “alternative embodiment”,and the like are intended to mean that any such features are included inone or more embodiments of the present disclosure, but may or may notnecessarily be combined in the same embodiments. Also, as used herein,including in the claims, “or” as used in a list of items (for example, alist of items prefaced by a phrase such as “at least one of” or “one ormore of”) indicates an inclusive list such that, for example, a list of[at least one of A, B, or C] means A or B or C or AB or AC or BC or ABC(i.e., A and B and C).

Various aspects of the illustrative embodiments are described usingterms commonly employed by those skilled in the art to convey thesubstance of their work to others skilled in the art. For example, theterm “connected” means a direct electrical connection between the thingsthat are connected, without any intermediary devices/components, whilethe term “coupled” means either a direct electrical connection betweenthe things that are connected, or an indirect connection through one ormore passive or active intermediary devices/components. In anotherexample, the term “circuit” means one or more passive and/or activecomponents that are arranged to cooperate with one another to provide adesired function. Also, as used herein, the terms “substantially,”“approximately,” “about,” etc., may be used to generally refer to beingwithin +/−20% of a target value, e.g., within +/−10% of a target value,based on the context of a particular value as described herein or asknown in the art.

Numerous other changes, substitutions, variations, alterations, andmodifications may be ascertained to one skilled in the art and it isintended that the present disclosure encompass all such changes,substitutions, variations, alterations, and modifications as fallingwithin the scope of the examples and appended claims. Note that alloptional features of the apparatus described above may also beimplemented with respect to the method or process described herein andspecifics in the examples may be used anywhere in one or moreembodiments.

The invention claimed is:
 1. An apparatus comprising: frequency dividercircuitry comprising: a first node to receive an input signal;fractional divider circuitry to generate, based on the input signal anda frequency-division ratio, a first signal having a first series ofpulses with adjacent pulses triggered by opposite edges of the inputsignal, wherein the fractional divider circuitry comprises first signalselection circuitry; balancer divider circuitry to generate, based onthe input signal, a second signal having a second series of pulsesaligned to the first series of pulses, wherein the balancer dividercircuitry comprises second signal selection circuitry triggered byopposite edges of the input signal than the first signal selectioncircuitry; and a second node to combine the first signal and the secondsignal.
 2. The apparatus of claim 1, wherein the balancer dividercircuitry generates the second signal using the same frequency-divisionratio as the fractional divider circuitry.
 3. The apparatus of claim 1,wherein the frequency-division ratio is 1.5.
 4. The apparatus of claim1, wherein: each of the first signal selection circuitry and the secondsignal selection circuitry has a respective first input, a respectivesecond input, and a respective output; the first signal selectioncircuitry switches from selecting the first respective input toselecting the second respective input responsive to one of a firstrising edge or a first falling edge of the input signal; and the secondsignal selection circuitry switches from selecting the respective firstinput to selecting the respective second input responsive to the otherone of the first rising edge or the first falling edge of the inputsignal.
 5. The apparatus of claim 4, wherein the first signal selectioncircuitry and the second signal selection circuitry have the samecircuit topology.
 6. The apparatus of claim 4, wherein: the fractionaldivider circuitry further comprises first dual edge-triggered circuitryto generate a third signal and a fourth signal responsive respectivelyto the first falling edge and the first rising edge of the input signal,third signal and the fourth signal received respectively at therespective first input and the respective second input of the firstsignal selection circuitry; and the balancer divider circuitry furthercomprises second dual edge-triggered circuitry to generate a fifthsignal and a sixth signal responsive respectively to the first risingedge and the first falling edge of the input signal, the fifth signaland the sixth signal received respectively at the respective first inputand the respective second input of the second signal selectioncircuitry.
 7. The apparatus of claim 1, wherein: the fractional dividercircuitry further comprises feedback circuitry to generate a feedbacksignal based on the combined first signal and second signal; thefractional divider circuitry generates the first signal further based onthe feedback signal; and the balancer divider circuitry generates thesecond signal further based on the feedback signal.
 8. The apparatus ofclaim 1, wherein the frequency divider circuitry further comprises: dutycycle correction circuitry to adjust a duty cycle of the combined firstsignal and second signal based on a feedback indicative of dutyinformation of the combined first signal and second signal and a targetduty cycle.
 9. An apparatus comprising: frequency divider circuitrycomprising: an input node to receive an input signal; fractional dividercircuitry to generate a frequency-divided signal from the input signal,wherein adjacent pulses in the frequency-divided signal are triggered byopposite edges of the input signal; and duty cycle correctiondelay-locked loop (DLL) to adjust a duty cycle of the frequency-dividedsignal.
 10. The apparatus of claim 9, wherein the duty cycle DLL:generate a rising edge of a duty cycle-adjusted signal from a risingedge of the frequency-divided signal; and generates a falling edge ofthe duty cycle-adjusted signal based on an error signal indicative ofduty cycle information of the frequency-divided signal.
 11. Theapparatus of claim 10, wherein the duty cycle DLL comprises: a filter tooutput a direct current (DC) component of the frequency-divided signal;and an amplifier having: a first input to receive the DC component ofthe frequency-divided signal; a second input to receive a referencevoltage; and an output to output the error signal; and a variable delayline controlled by the error signal to generate a feedback signal. 12.The apparatus of claim 11, wherein the reference voltage at the secondinput of the amplifier is half of a supply voltage.
 13. The apparatus ofclaim 11, wherein the reference voltage at the second input of theamplifier is configured based on a target duty cycle.
 14. The apparatusof claim 11, wherein the duty cycle correction DLL generates the fallingedge of the duty cycle-adjusted signal further from a rising edge of thefeedback signal.
 15. The apparatus of claim 11, wherein the duty cycleDLL generates the falling edge of the duty cycle-adjusted signal furtherby gating a falling edge of the frequency-divided signal by the feedbacksignal.
 16. The apparatus of claim 9, further comprising: balancerdivider circuitry to generate a first signal having a same phase as thefrequency-divided signal, wherein the balancer divider circuitrycomprises a first multiplexer that is triggered by opposite edges of theinput signal than a second multiplexer in the fractional dividercircuitry; and a summing node to add the first signal to thefrequency-divided signal.
 17. An integrated circuit device, comprising:frequency synthesizer circuitry comprising: a voltage-controlledoscillator (VCO) to generate a reference clock signal; frequency dividercircuitry to divide a frequency of the reference clock signal by afractional division ratio to generate a first signal; and subharmoniccancellation circuitry to: generate a second signal having the samephase as the first signal; and combine the first signal and the secondsignal to generate a third signal having a reduced sub-harmonic than thefirst signal, wherein the subharmonic cancellation circuitry comprises areplica circuit replicating a first circuit of the frequency dividercircuitry, wherein the replica circuit is triggered by opposite edges ofthe reference clock signal than the first circuit; and duty cyclecorrection circuitry to adjust a duty cycle of the third signal togenerate a duty cycle-corrected signal.
 18. The integrated circuitdevice of claim 17, wherein: the first circuit of the frequency dividercircuitry comprises a first multiplexer; the replica circuit of thesubharmonic cancellation circuitry comprises a second multiplexer; eachof the first multiplexer and the second multiplexer has a respectivefirst input, a respective second input, and a respective output; thefirst multiplexer switches from selecting the first respective input toselecting the second respective input responsive to one of a rising edgeor a falling edge of the reference clock signal; and the secondmultiplexer switches from selecting the respective first input toselecting the respective second input responsive to the other one of therising edge or the falling edge of the reference clock signal.
 19. Theintegrated circuit device of claim 17, wherein the duty cycle correctioncircuitry adjusts the duty cycle of the third signal by: generating arising edge of the duty cycle-corrected signal from a rising edge of thethird signal; generating a falling edge the duty cycle-corrected signalfrom a rising edge of a feedback signal; and generating the feedbacksignal by delaying the third signal by a delay associated with a dutycycle of the third signal.
 20. The integrated circuit device of claim17, wherein the duty cycle correction circuitry adjusts the duty cycleof the third signal by: generating a rising edge of the dutycycle-corrected signal from a rising edge of the third signal;generating a falling edge the duty cycle-corrected signal by gating afalling edge of the third signal by a rising edge of a feedback signal;and generating the feedback signal by delaying the third signal by adelay associated with a duty cycle of the third signal.